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MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 mixed signal microcontroller 1 features 23 ? low supply voltage range: 1.8 v to 3.6 v ? brownout detector ? ultra-low power consumption ? serial onboard programming, no external programming voltage needed, ? active mode: 220 a at 1 mhz, 2.2 v programmable code protection by security ? standby mode: 0.5 a fuse ? off mode (ram retention): 0.1 a ? on-chip emulation logic with spy-bi-wire ? five power-saving modes interface ? ultra-fast wake-up from standby mode in ? family members are summarized in table 1 less than 1 s ? package options ? 16-bit risc architecture, 62.5-ns instruction ? tssop: 20 pin cycle time ? for complete module descriptions, see the ? basic clock module configurations msp430x2xx family user ? s guide ( slau144 ) ? internal frequencies up to 16 mhz with four calibrated frequencies supports defense, aerospace, ? internal very-low-power low-frequency and medical applications (lf) oscillator ? controlled baseline ? 32-khz crystal (1) ? one assembly and test site ? external digital clock source ? one fabrication site ? one 16-bit timer_a with three ? available in extended ( ? 40 c to 125 c) capture/compare registers temperature range (2) ? up to 16 touch-sense enabled i/o pins ? extended product life cycle ? universal serial interface (usi) supporting spi ? extended product-change notification and i2c (see table 1 ) ? product traceability ? 10-bit 200-ksps analog-to-digital (a/d) converter with internal reference, sample- and-hold, and autoscan (see table 1 ) (1) crystal oscillator cannot be operated beyond 105 c (2) custom temperature ranges available description the texas instruments msp430 ? family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. the architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. the device features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the digitally controlled oscillator (dco) allows wake-up from low-power modes to active mode in less than 1 s. the msp430g2332 series of microcontrollers are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, and up to 16 i/o touch sense enabled pins and built-in communication capability using the universal serial communication interface. the msp430g2332 series have a 10-bit a/d converter. for configuration details, see table 1 . typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 msp430 is a trademark of texas instruments. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2012, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com table 1. available options flash ram adc10 device eem timer_a usi clock i/o package type (kb) (b) channel msp430g2332qpw2ep 1 4 256 1x ta3 8 1 lf, dco, vlo 16 20-tssop table 2. ordering information (1) t a package orderable part number top-side marking vid number msp430g2332qpw2rep tape and reel, 2000 v62/12625-01xe ? 40 c to 125 c tssop - pw g2332ep msp430g2332qpw2ep tube, 70 v62/12625-01xe-t (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . 2 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. device pinouts pw package (top view) copyright ? 2012, texas instruments incorporated submit documentation feedback 3 1 dvcc 2 p1.0/ta0clk/aclk/a0 3 4 5 p1.3/adc10clk/vref-/veref-/a3 6 7 8 p2.0 9 p2.1 10 p2.2 11 p2.3 12 p2.4 13 p2.5 14 15 16 rst/nmi/sbwtdio 17 test/sbwtck 18 xout/p2.7 19 xin/p2.6/ta0.1 20 dvss p1.6/ta0.1/ tdi/tclk sdo/scl/a6/ p1.7/sdi/sda/a7/tdo/tdi p1.1/ta0.0/a1 p1.2/ta0.1/a2 p1.4/ta0.2/smclk/a4/ /tck vref+/veref+ p1.5/ta0.0 a5/tms /sclk/
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com functional block diagrams functional block diagram note: port p2: two pins are available on the 14-pin package option. eight pins are available on the 20-pin package option. 4 submit documentation feedback copyright ? 2012, texas instruments incorporated clock system brownout protection rst/nmi dvcc dvss mclk watchdog wdt+ 15-bit timer0_a3 3 cc registers 16mhz cpu incl. 16 registers emulation 2bp jtag interface smclk aclk mdb mab port p1 8 i/o interrupt capability pullup/down resistors p1.x 8 spy-bi wire xin xout ram 256b 256b 256b 128b flash 8kb 4kb 2kb 1kb p2.x port p2 up to 8 i/o interrupt capability pullup/down resistors up to 8 usi universal serial interface spi, i2c adc 10-bit 8 ch. autoscan 1 ch dma
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 terminal functions table 3. terminal functions terminal no. i/o description name pw20 p1.0/ general-purpose digital i/o pin ta0clk/ timer0_a, clock signal taclk input 2 i/o aclk/ aclk signal output a0 adc10 analog input a0 p1.1/ general-purpose digital i/o pin ta0.0/ 3 i/o timer0_a, capture: cci0a input, compare: out0 output a1 adc10 analog input a1 p1.2/ general-purpose digital i/o pin ta0.1/ 4 i/o timer0_a, capture: cci1a input, compare: out1 output a2 adc10 analog input a2 p1.3/ general-purpose digital i/o pin adc10clk/ adc10, conversion clock output 5 i/o a3/ adc10 analog input a3 vref-/veref adc10 negative reference voltage p1.4/ general-purpose digital i/o pin ta0.2/ timer0_a, capture: cci2a input, compare: out2 output smclk/ smclk signal output 6 i/o a4/ adc10 analog input a4 vref+/veref+/ adc10 positive reference voltage tck jtag test clock, input terminal for device programming and test p1.5/ general-purpose digital i/o pin ta0.0/ timer0_a, compare: out0 output a5/ 7 i/o adc10 analog input a5 sclk/ usi: clk input in i2c mode; clk in/output in spi mode tms jtag test mode select, input terminal for device programming and test p1.6/ general-purpose digital i/o pin ta0.1/ timer0_a, compare: out1 output a6/ adc10 analog input a6 sdo/ 14 i/o usi: data output in spi mode scl/ usi: i2c clock in i2c mode tdi/ jtag test data input or test clock input during programming and test tclk p1.7/ general-purpose digital i/o pin a7/ adc10 analog input a7 sdi/ 15 i/o usi: data input in spi mode sda/ usi: i2c data in i2c mode tdo/tdi (1) jtag test data output terminal or test data input during programming and test p2.0 8 i/o general-purpose digital i/o pin p2.1 9 i/o general-purpose digital i/o pin p2.2 10 i/o general-purpose digital i/o pin p2.3 11 i/o general-purpose digital i/o pin p2.4 12 i/o general-purpose digital i/o pin p2.5 13 i/o general-purpose digital i/o pin (1) tdo or tdi is selected via jtag instruction. copyright ? 2012, texas instruments incorporated submit documentation feedback 5
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com table 3. terminal functions (continued) terminal no. i/o description name pw20 xin/ input terminal of crystal oscillator p2.6/ 19 i/o general-purpose digital i/o pin ta0.1 timer0_a, compare: out1 output xout/ output terminal of crystal oscillator (2) 18 i/o p2.7 general-purpose digital i/o pin rst/ reset nmi/ 16 i nonmaskable interrupt input sbwtdio/ spy-bi-wire test data input/output during programming and test test/ selects test mode for jtag pins on port 1. the device protection fuse is connected to test. 17 i sbwtck spy-bi-wire test clock input during programming and test dvcc 1 na supply voltage avcc na na supply voltage dvss 20 na ground reference avss na na ground reference nc - na not connected qfn pad - na qfn package pad connection to vss recommended. (2) if xout/p2.7 is used as an input, excess current flows until p2sel.7 is cleared. this is due to the oscillator output driver connection to this pad after reset. 6 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 short-form description cpu the msp430 ? cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to- register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. the instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. each instruction can operate on word and byte data. instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 4 shows examples of the three types of instruction formats; table 5 shows the address modes. table 4. instruction word formats format example operation dual operands, source-destination add r4,r5 r4 + r5 r5 single operands, destination only call r8 pc (tos), r8 pc relative jump, un/conditional jne jump-on-equal bit = 0 table 5. address mode descriptions (1) address mode s d syntax example operation register ? ? mov rs,rd mov r10,r11 r10 r11 indexed ? ? mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5) m(6+r6) symbolic (pc relative) ? ? mov ede,toni m(ede) m(toni) absolute ? ? mov & mem, & tcdat m(mem) m(tcdat) indirect ? mov @rn,y(rm) mov @r10,tab(r6) m(r10) m(tab+r6) m(r10) r11 indirect autoincrement ? mov @rn+,rm mov @r10+,r11 r10 + 2 r10 immediate ? mov #x,toni mov #45,toni #45 m(toni) (1) s = source, d = destination copyright ? 2012, texas instruments incorporated submit documentation feedback 7 general-purpose register program counter stack pointer status register constant generator general-purpose register general-purpose register general-purpose register pc/r0sp/r1 sr/cg1/r2 cg2/r3 r4 r5 r12 r13 general-purpose register general-purpose register r6r7 general-purpose register general-purpose register r8r9 general-purpose register general-purpose register r10 r11 general-purpose register general-purpose register r14 r15
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com operating modes the msp430 devices have one active mode and five software selectable low-power modes of operation. an interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: ? active mode (am) ? all clocks are active ? low-power mode 0 (lpm0) ? cpu is disabled ? aclk and smclk remain active, mclk is disabled ? low-power mode 1 (lpm1) ? cpu is disabled ? aclk and smclk remain active, mclk is disabled ? dco's dc generator is disabled if dco not used in active mode ? low-power mode 2 (lpm2) ? cpu is disabled ? mclk and smclk are disabled ? dco's dc generator remains enabled ? aclk remains active ? low-power mode 3 (lpm3) ? cpu is disabled ? mclk and smclk are disabled ? dco's dc generator is disabled ? aclk remains active ? low-power mode 4 (lpm4) ? cpu is disabled ? aclk is disabled ? mclk and smclk are disabled ? dco's dc generator is disabled ? crystal oscillator is stopped 8 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 interrupt vector addresses the interrupt vectors and the power-up starting address are located in the address range 0ffffh to 0ffc0h. the vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. if the reset vector (located at address 0fffeh) contains 0ffffh (for example, if flash is not programmed) the cpu goes into lpm4 immediately after power-up. table 6. interrupt sources, flags, and vectors system word interrupt source interrupt flag priority interrupt address power-up porifg external reset rstifg watchdog timer+ wdtifg reset 0fffeh 31, highest flash key violation keyv (2) pc out-of-range (1) nmi nmiifg (non)-maskable oscillator fault ofifg (non)-maskable 0fffch 30 flash memory access violation accvifg (2) (3) (non)-maskable 0fffah 29 0fff8h 28 0fff6h 27 watchdog timer+ wdtifg maskable 0fff4h 26 timer0_a3 taccr0 ccifg (4) maskable 0fff2h 25 timer0_a3 taccr2 taccr1 ccifg. maskable 0fff0h 24 taifg table 4 (4) 0ffeeh 23 0ffech 22 adc10 adc10ifg (4) maskable 0ffeah 21 usi usiifg, usisttifg (2) (4) maskable 0ffe8h 20 i/o port p2 (up to eight flags) p2ifg.0 to p2ifg.7 (2) (4) maskable 0ffe6h 19 i/o port p1 (up to eight flags) p1ifg.0 to p1ifg.7 (2) (4) maskable 0ffe4h 18 0ffe2h 17 0ffe0h 16 see (5) 0ffdeh to 15 to 0, lowest 0ffc0h (1) a reset is generated if the cpu tries to fetch instructions from within the module register memory address range (0h to 01ffh) or from within unused address ranges. (2) multiple source flags (3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. (4) interrupt flags are located in the module. (5) the interrupt vectors at addresses 0ffdeh to 0ffc0h are not used in this device and can be used for regular program code if necessary. copyright ? 2012, texas instruments incorporated submit documentation feedback 9
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com special function registers (sfrs) most interrupt and module enable bits are collected into the lowest address space. special function register bits not allocated to a functional purpose are not physically present in the device. simple software access is provided with this arrangement. legend rw: bit can be read and written. rw-0,1: bit can be read and written. it is reset or set by puc. rw-(0,1): bit can be read and written. it is reset or set by por. sfr bit is not present in device. table 7. interrupt enable register 1 and 2 address 7 6 5 4 3 2 1 0 00h accvie nmiie ofie wdtie rw-0 rw-0 rw-0 rw-0 wdtie watchdog timer interrupt enable. inactive if watchdog mode is selected. active if watchdog timer is configured in interval timer mode. ofie oscillator fault interrupt enable nmiie (non)maskable interrupt enable accvie flash access violation interrupt enable address 7 6 5 4 3 2 1 0 01h table 8. interrupt flag register 1 and 2 address 7 6 5 4 3 2 1 0 02h nmiifg rstifg porifg ofifg wdtifg rw-0 rw-(0) rw-(1) rw-1 rw-(0) wdtifg set on watchdog timer overflow (in watchdog mode) or security key violation. reset on v cc power-on or a reset condition at the rst/nmi pin in reset mode. ofifg flag set on oscillator fault. porifg power-on reset interrupt flag. set on v cc power-up. rstifg external reset interrupt flag. set on a reset condition at rst/nmi pin in reset mode. reset on v cc power-up. nmiifg set via rst/nmi pin address 7 6 5 4 3 2 1 0 03h 10 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 memory organization table 9. memory organization msp430g2332 memory size 4kb main: interrupt vector flash 0xffff to 0xffc0 main: code memory flash 0xffff to 0xf000 information memory size 256 byte flash 010ffh to 01000h ram size 256 b 0x02ff to 0x0200 peripherals 16-bit 01ffh to 0100h 8-bit 0ffh to 010h 8-bit sfr 0fh to 00h flash memory the flash memory can be programmed via the spy-bi-wire/jtag port or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: ? flash memory has n segments of main memory and four segments of information memory (a to d) of 64 bytes each. each segment in main memory is 512 bytes in size. ? segments 0 to n may be erased in one step, or each segment may be individually erased. ? segments a to d can be erased individually or as a group with segments 0 to n. segments a to d are also called information memory . ? segment a contains calibration data. after reset, segment a is protected against programming and erasing. it can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. copyright ? 2012, texas instruments incorporated submit documentation feedback 11
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com peripherals peripherals are connected to the cpu through data, address, and control buses and can be handled using all instructions. for complete module descriptions, see the msp430x2xx family user's guide ( slau144 ). oscillator and system clock the clock system is supported by the basic clock module that includes support for a 32768-hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, and an internal digitally controlled oscillator (dco). the basic clock module is designed to meet the requirements of both low system cost and low power consumption. the internal dco provides a fast turn-on clock source and stabilizes in less than 1 s. the basic clock module provides the following clock signals: ? auxiliary clock (aclk), sourced either from a 32768-hz watch crystal or the internal lf oscillator. ? main clock (mclk), the system clock used by the cpu. ? sub-main clock (smclk), the sub-system clock used by the peripheral modules. the dco settings to calibrate the dco output frequency are stored in the information memory segment a. calibration data stored in information memory segment a calibration data is stored for both the dco and for adc10 organized in a tag-length-value structure. table 10. tags used by the adc calibration tags name address value description tag_dco_30 0x10f6 0x01 dco frequency calibration at v cc = 3 v and t a = 30 c at calibration tag_adc10_1 0x10da 0x10 adc10_1 calibration tag tag_empty - 0xfe identifier for empty memory areas table 11. labels used by the adc calibration tags label condition at calibration / description size address offset cal_adc_25t85 inchx = 0x1010, ref2_5 = 1, t a = 85 c word 0x0010 cal_adc_25t30 inchx = 0x1010, ref2_5 = 1, t a = 30 c word 0x000e cal_adc_25vref_factor ref2_5 = 1, t a = 30 c, i (vref+) = 1 ma word 0x000c cal_adc_15t85 inchx = 0x1010, ref2_5 = 0, t a = 85 c word 0x000a cal_adc_15t30 inchx = 0x1010, ref2_5 = 0, t a = 30 c word 0x0008 cal_adc_15vref_factor ref2_5 = 0, t a = 30 c, i (vref+) = 0.5 ma word 0x0006 cal_adc_offset external vref = 1.5 v, f (adc10clk) = 5 mhz word 0x0004 cal_adc_gain_factor external vref = 1.5 v, f (adc10clk) = 5 mhz word 0x0002 cal_bc1_1mhz - byte 0x0009 cal_dco_1mhz - byte 0x00008 cal_bc1_8mhz - byte 0x0007 cal_dco_8mhz - byte 0x0006 cal_bc1_12mhz - byte 0x0005 cal_dco_12mhz - byte 0x0004 cal_bc1_16mhz - byte 0x0003 cal_dco_16mhz - byte 0x0002 12 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 main dco characteristics ? all ranges selected by rselx overlap with rselx + 1: rselx = 0 overlaps rselx = 1, ... rselx = 14 overlaps rselx = 15. ? dco control bits dcox have a step size as defined by parameter s dco . ? modulation control bits modx select how often f dco(rsel,dco+1) is used within the period of 32 dcoclk cycles. the frequency f dco(rsel,dco) is used for the remaining cycles. the frequency is an average equal to: brownout the brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. digital i/o there are two 8-bit i/o ports implemented: ? all individual i/o bits are independently programmable. ? any combination of input, output, and interrupt condition(port p1 and port p2 only) is possible. ? edge-selectable interrupt input capability for all the eight bits of port p1 and port p2, if available. ? read/write access to port-control registers is supported by all instructions. ? each i/o has an individually programmable pullup/pulldown resistor. ? each i/o has an individually programmable pin-oscillator enable bit to enable low-cost touch sensing. wdt+ watchdog timer the primary function of the watchdog timer (wdt+) module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. copyright ? 2012, texas instruments incorporated submit documentation feedback 13 dco(rsel,dco+1) dco(rsel,dco) average dco(rsel,dco) dco(rsel,dco+1) 32 f f f = mod f + (32 C mod) f
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com timer0_a3 timer0_a3 is a 16-bit timer/counter with three capture/compare registers. timer0_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer0_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 12. timer0_a3 signal connections (1) output pin input pin number device input module input module output number module block signal name signal pw20 pw20 p1.0-2 taclk taclk aclk aclk timer na smclk smclk pinosc inclk p1.1-3 ta0.0 cci0a p1.1-3 aclk cci0b p1.5-7 ccr0 ta0 v ss gnd v cc v cc p1.2-4 ta0.1 cci1a p1.2-4 caout cci1b p1.6-14 ccr1 ta1 v ss gnd p2.6-19 v cc v cc p1.4-6 ta0.2 cci2a p1.4-6 pinosc ta0.2 cci2b ccr2 ta2 v ss gnd v cc v cc (1) only one pin-oscillator must be enabled at a time. usi the universal serial interface (usi) module is used for serial data communication and provides the basic hardware for synchronous communication protocols like spi and i2c. adc10 the adc10 module supports fast, 10-bit analog-to-digital conversions. the module implements a 10-bit sar core, sample select control, reference generator and data transfer controller, or dtc, for automatic conversion result handling, allowing adc samples to be converted and stored without any cpu intervention. 14 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 peripheral file map table 13. peripherals with word access register module register description offset name adc10 adc data transfer start address adc10sa 01bch adc memory adc10mem 01b4h adc control register 1 adc10ctl1 01b2h adc control register 0 adc10ctl0 01b0h timer0_a3 capture/compare register taccr2 0176h capture/compare register taccr1 0174h capture/compare register taccr0 0172h timer_a register tar 0170h capture/compare control tacctl2 0166h capture/compare control tacctl1 0164h capture/compare control tacctl0 0162h timer_a control tactl 0160h timer_a interrupt vector taiv 012eh flash memory flash control 3 fctl3 012ch flash control 2 fctl2 012ah flash control 1 fctl1 0128h watchdog timer+ watchdog/timer control wdtctl 0120h copyright ? 2012, texas instruments incorporated submit documentation feedback 15
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com table 14. peripherals with byte access register module register description offset name adc10 analog enable 0 adc10ae0 04ah adc data transfer control register 1 adc10dtc1 049h adc data transfer control register 0 adc10dtc0 048h usi usi control 0 usictl0 078h usi control 1 usictl1 079h usi clock control usickctl 07ah usi bit counter usicnt 07bh usi shift register usisr 07ch basic clock system+ basic clock system control 3 bcsctl3 053h basic clock system control 2 bcsctl2 058h basic clock system control 1 bcsctl1 057h dco clock frequency control dcoctl 056h port p2 port p2 selection 2 p2sel2 042h port p2 resistor enable p2ren 02fh port p2 selection p2sel 02eh port p2 interrupt enable p2ie 02dh port p2 interrupt edge select p2ies 02ch port p2 interrupt flag p2ifg 02bh port p2 direction p2dir 02ah port p2 output p2out 029h port p2 input p2in 028h port p1 port p1 selection 2 p1sel2 041h port p1 resistor enable p1ren 027h port p1 selection p1sel 026h port p1 interrupt enable p1ie 025h port p1 interrupt edge select p1ies 024h port p1 interrupt flag p1ifg 023h port p1 direction p1dir 022h port p1 output p1out 021h port p1 input p1in 020h special function sfr interrupt flag 2 ifg2 003h sfr interrupt flag 1 ifg1 002h sfr interrupt enable 2 ie2 001h sfr interrupt enable 1 ie1 000h 16 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 absolute maximum ratings (1) voltage applied at v cc to v ss ? 0.3 v to 4.1 v voltage applied to any pin (2) ? 0.3 v to v cc + 0.3 v diode current at any device pin 2 ma unprogrammed device ? 55 c to 150 c storage temperature range, t stg (3) programmed device ? 55 c to 150 c (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages referenced to v ss . the jtag fuse-blow voltage, v fb , is allowed to exceed the absolute maximum rating. the voltage is applied to the test pin when blowing the jtag fuse. (3) higher temperature may be applied during board soldering according to the current jedec j-std-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. xxx a. see data sheet for absolute maximum and minimum recommended operating conditions. b. silicon operating life design goal is 10 years at 110 c junction temperature (does not include package interconnect life). c. the predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics. figure 1. operating life derating chart copyright ? 2012, texas instruments incorporated submit documentation feedback 17
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com thermal information MSP430G2332-EP thermal metric (1) pw units 20 pins ja junction-to-ambient thermal resistance (2) 98.7 jctop junction-to-case (top) thermal resistance (3) 26.8 jb junction-to-board thermal resistance (4) 41.2 c/w jt junction-to-top characterization parameter (5) 1.1 jb junction-to-board characterization parameter (6) 40.5 jcbot junction-to-case (bottom) thermal resistance (7) n/a (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) the junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a jedec-standard, high-k board, as specified in jesd51-7, in an environment described in jesd51-2a. (3) the junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. no specific jedec- standard test exists, but a close description can be found in the ansi semi standard g30-88. (4) the junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the pcb temperature, as described in jesd51-8. (5) the junction-to-top characterization parameter, jt , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (6) the junction-to-board characterization parameter, jb , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (7) the junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. no specific jedec standard test exists, but a close description can be found in the ansi semi standard g30-88. spacer 18 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 recommended operating conditions min nom max unit during program execution 1.8 3.6 v cc supply voltage v during flash programming/erase 2.2 3.6 v ss supply voltage 0 v t a operating free-air temperature -40 125 c v cc = 1.8 v, dc 6 duty cycle = 50% 10% processor frequency (maximum mclk frequency v cc = 2.7 v, f system dc 12 mhz using the usart module) (1) (2) duty cycle = 50% 10% v cc = 3.3 v, dc 16 duty cycle = 50% 10% (1) the msp430 cpu is clocked directly with mclk. both the high and low phase of mclk must not exceed the pulse width of the specified maximum frequency. (2) modules might have a different maximum input clock specification. see the specification of the respective module in this data sheet. note: minimum processor frequency is defined by system clock. flash program or erase operations require a minimum v cc of 2.2 v. figure 2. safe operating area copyright ? 2012, texas instruments incorporated submit documentation feedback 19 supply voltage range, during flash memory programming supply voltage range, during program execution legend : 16 mhz system frequency - mhz 12 mhz 6 mhz 1.8 v supply voltage - v 3.3 v 2.7 v 2.2 v 3.6 v
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com electrical characteristics active mode supply current into v cc excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) parameter test conditions v cc min typ max unit f dco = f mclk = f smclk = 1 mhz, 2.2 v 220 f aclk = 32768 hz, program executes in flash, active mode (am) i am,1mhz bcsctl1 = calbc1_1mhz, a current (1 mhz) 3 v 320 400 dcoctl = caldco_1mhz, cpuoff = 0, scg0 = 0, scg1 = 0, oscoff = 0 (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) the currents are characterized with a micro crystal cc4v-t1a smd crystal with a load capacitance of 9 pf. the internal and external load capacitance is chosen to closely match the required 9 pf. typical characteristics ? active mode supply current (into v cc ) figure 3. active mode current vs v cc , t a = 25 c figure 4. active mode current vs dco frequency 20 submit documentation feedback copyright ? 2012, texas instruments incorporated 0.0 1.0 2.0 3.0 4.0 5.0 1.5 2.0 2.5 3.0 3.5 4.0 v cc ? supply voltage ? v active mode current ? ma f dco = 1 mhz f dco = 8 mhz f dco = 12 mhz f dco = 16 mhz 0.0 1.0 2.0 3.0 4.0 0.0 4.0 8.0 12.0 16.0 f dco ? dco frequency ? mhz active mode current ? ma t a = 25 c t a = 85 c v cc = 2.2 v v cc = 3 v t a = 25 c t a = 85 c
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 low-power mode supply currents (into v cc ) excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions t a v cc min typ max unit f mclk = 0 mhz, f smclk = f dco = 1 mhz, f aclk = 32768 hz, low-power mode 0 i lpm0,1mhz bcsctl1 = calbc1_1mhz, 25 c 2.2 v 55 a (lpm0) current (2) dcoctl = caldco_1mhz, cpuoff = 1, scg0 = 0, scg1 = 0, oscoff = 0 f mclk = f smclk = 0 mhz, f dco = 1 mhz, f aclk = 32768 hz, low-power mode 2 i lpm2 bcsctl1 = calbc1_1mhz, 25 c 2.2 v 22 a (lpm2) current (3) dcoctl = caldco_1mhz, cpuoff = 1, scg0 = 0, scg1 = 1, oscoff = 0 f dco = f mclk = f smclk = 0 mhz, 25 c 0.7 1.5 low-power mode 3 f aclk = 32768 hz, i lpm3,lfxt1 2.2 v a (lpm3) current (3) cpuoff = 1, scg0 = 1, scg1 = 1, 125 c 24 oscoff = 0 f dco = f mclk = f smclk = 0 mhz, 25 c 0.5 0.7 low-power mode 3 f aclk from internal lf oscillator (vlo), i lpm3,vlo 2.2 v a current, (lpm3) (3) cpuoff = 1, scg0 = 1, scg1 = 1, 125 c 3 9.3 oscoff = 0 f dco = f mclk = f smclk = 0 mhz, 25 c 0.1 0.5 a low-power mode 4 f aclk = 0 hz, 85 c 0.8 1.5 i lpm4 2.2 v (lpm4) current (4) cpuoff = 1, scg0 = 1, scg1 = 1, a 125 c 3 8 oscoff = 1 (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) current for brownout and wdt clocked by smclk included. (3) current for brownout and wdt clocked by aclk included. (4) current for brownout included. typical characteristics low-power mode supply currents over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) figure 5. lpm3 current vs temperature figure 6. lpm4 current vs temperature copyright ? 2012, texas instruments incorporated submit documentation feedback 21 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?40.0 ?20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 t a ? temperature ? c v = 3.6 v cc t a ? temperature ? c i ? low?power mode current ? a lpm4 v = 1.8 v cc v = 3 v cc v = 2.2 v cc 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 ?40.0 ?20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 i ? low?power mode current ? a lpm3 v = 3.6 v cc t a ? temperature ? c v = 1.8 v cc v = 3 v cc v = 2.2 v cc
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com schmitt-trigger inputs ? ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 0.45 v cc 0.75 v cc v it+ positive-going input threshold voltage v 3 v 1.35 2.25 0.25 v cc 0.55 v cc v it ? negative-going input threshold voltage v 3 v 0.75 1.65 v hys input voltage hysteresis (v it+ ? v it ? ) 3 v 0.3 1 v for pullup: v in = v ss r pull pullup/pulldown resistor 3 v 20 35 50 k ? for pulldown: v in = v cc c i input capacitance v in = v ss or v cc 5 pf leakage current ? ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit t a = -40 c to 85 c 50 i lkg(px.x) high-impedance leakage current (1) (2) 3 v na t a = 125 c (1) (2) 120 (1) the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. (2) the leakage of the digital port pins is measured individually. the port pin is selected for input, and the pullup/pulldown resistor is disabled. outputs ? ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v oh high-level output voltage i (ohmax) = ? 6 ma (1) 3 v v cc ? 0.3 v v ol low-level output voltage i (olmax) = 6 ma (1) 3 v v ss + 0.3 v (1) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined should not exceed 48 ma to hold the maximum voltage drop specified. output frequency ? ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f px.y port output frequency (with load) px.y, c l = 20 pf, r l = 1 k (1) (2) 3 v 12 mhz f port_clk clock output frequency px.y, c l = 20 pf (2) 3 v 16 mhz (1) a resistive divider with two 0.5-k resistors between v cc and v ss is used as load. the output is connected to the center tap of the divider. (2) the output voltage reaches at least 10% and 90% v cc at the specified toggle frequency. 22 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 typical characteristics ? outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) figure 7. figure 8. figure 9. figure 10. copyright ? 2012, texas instruments incorporated submit documentation feedback 23 v oh ? high-level output voltage ? v ?25.0 ?20.0 ?15.0 ?10.0 ?5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.7 typical high-level output current vs high-level output voltage t a = 25c t a = 85c oh i ? typical high-level output current ? ma v oh ? high-level output voltage ? v ?50.0 ?40.0 ?30.0 ?20.0 ?10.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.7 typical high-level output current vs high-level output voltage t a = 25c t a = 85c oh i ? typical high-level output current ? ma v ol ? low-level output voltage ? v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.7 typical low -level output current vs low-level output vol tage t a = 25c t a = 85c ol i ? typical low-level output current ? ma v ol ? low-level output voltage ? v 0.0 10.0 20.0 30.0 40.0 50.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.7 typical low -level output current vs low-level output vol tage t a = 25c t a = 85c ol i ? typical low-level output current ? ma
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com pin-oscillator frequency ? ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit p1.y, c l = 10 pf, r l = 100 k (1) (2) 1400 fo p1.x port output oscillation frequency 3 v khz p1.y, c l = 20 pf, r l = 100 k (1) (2) 900 p2.0 to p2.5, c l = 10 pf, r l = 100 k (1) (2) 1800 fo p2.x port output oscillation frequency 3 v khz p2.0 to p2.5, c l = 20 pf, r l = 100 k (1) (2) 1000 fo p2.6/7 port output oscillation frequency p2.6 and p2.7, c l = 20 pf, r l = 100 k (1) (2) 3 v 700 khz (1) a resistive divider with two 100-k resistors between v cc and v ss is used as load. the output is connected to the center tap of the divider. (2) the output voltage oscillates with a typical amplitude of 700 mv at the specified toggle frequency. typical characteristics ? pin-oscillator frequency figure 11. figure 12. 24 submit documentation feedback copyright ? 2012, texas instruments incorporated c load ? external capacitance ? pf 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 10 50 100 p1.y p2.0 ... p2.5 p2.6, p2.7 v cc = 2.2 v typical oscillating frequency vs load capacitance fosc ? typical oscillation frequency ? mhz c load ? external capacitance ? pf 0.00 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 10 50 100 p1.y p2.0 ... p2.5 p2.6, p2.7 v cc = 3.0 v typical oscillating frequency vs load capacitance fosc ? typical oscillation frequency ? mhz
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 por/brownout reset (bor) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v cc(start) see figure 13 dv cc /dt 3 v/s 0.7 v (b_it ? ) v v (b_it ? ) see figure 13 through figure 15 dv cc /dt 3 v/s 1.40 v v hys(b_it ? ) see figure 13 dv cc /dt 3 v/s 140 mv t d(bor) see figure 13 2000 s pulse length needed at rst/nmi pin to t (reset) 2.2 v 2 s accepted reset internally (2) (1) the current consumption of the brownout module is already included in the i cc current consumption data. the voltage level v (b_it ? ) + v hys(b_it ? ) is 1.8 v. (2) minimum and maximum parameters are characterized up to t a = 105 c, unless otherwise noted. figure 13. por/brownout reset (bor) vs supply voltage copyright ? 2012, texas instruments incorporated submit documentation feedback 25 0 1 t d(bor) v cc v (b_it?) v hys(b_it?) v cc(start)
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com typical characteristics ? por/brownout reset (bor) figure 14. v cc(drop) level with a square voltage drop to generate a por/brownout signal figure 15. v cc(drop) level with a triangle voltage drop to generate a por/brownout signal 26 submit documentation feedback copyright ? 2012, texas instruments incorporated v cc 0 0.5 1 1.5 2 v cc(drop) t pw t pw ? pulse width ? s v cc(drop) ? v 3 v 0.001 1 1000 t f t r t pw ? pulse width ? s t f = t r typical conditions v cc = 3 v v cc(drop) v cc 3 v t pw 0 0.5 1 1.5 2 0.001 1 1000 typical conditions 1 ns 1 ns t pw ? pulse width ? s v cc(drop) ? v t pw ? pulse width ? s v cc = 3 v
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 dco frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit rselx < 14 1.8 3.6 v v cc supply voltage rselx = 14 2.2 3.6 v rselx = 15 3 3.6 v f dco(0,0) dco frequency (0, 0) rselx = 0, dcox = 0, modx = 0 3 v 0.06 0.14 mhz f dco(0,3) dco frequency (0, 3) rselx = 0, dcox = 3, modx = 0 3 v 0.07 0.17 mhz f dco(1,3) dco frequency (1, 3) rselx = 1, dcox = 3, modx = 0 3 v 0.15 mhz f dco(2,3) dco frequency (2, 3) rselx = 2, dcox = 3, modx = 0 3 v 0.21 mhz f dco(3,3) dco frequency (3, 3) rselx = 3, dcox = 3, modx = 0 3 v 0.30 mhz f dco(4,3) dco frequency (4, 3) rselx = 4, dcox = 3, modx = 0 3 v 0.41 mhz f dco(5,3) dco frequency (5, 3) rselx = 5, dcox = 3, modx = 0 3 v 0.58 mhz f dco(6,3) dco frequency (6, 3) rselx = 6, dcox = 3, modx = 0 3 v 0.54 1.06 mhz f dco(7,3) dco frequency (7, 3) rselx = 7, dcox = 3, modx = 0 3 v 0.80 1.50 mhz f dco(8,3) dco frequency (8, 3) rselx = 8, dcox = 3, modx = 0 3 v 1.6 mhz f dco(9,3) dco frequency (9, 3) rselx = 9, dcox = 3, modx = 0 3 v 2.3 mhz f dco(10,3) dco frequency (10, 3) rselx = 10, dcox = 3, modx = 0 3 v 3.4 mhz f dco(11,3) dco frequency (11, 3) rselx = 11, dcox = 3, modx = 0 3 v 4.25 mhz f dco(12,3) dco frequency (12, 3) rselx = 12, dcox = 3, modx = 0 3 v 4.30 7.30 mhz f dco(13,3) dco frequency (13, 3) rselx = 13, dcox = 3, modx = 0 3 v 6.00 9.60 mhz f dco(14,3) dco frequency (14, 3) rselx = 14, dcox = 3, modx = 0 3 v 8.60 13.9 mhz f dco(15,3) dco frequency (15, 3) rselx = 15, dcox = 3, modx = 0 3 v 12.0 18.5 mhz f dco(15,7) dco frequency (15, 7) rselx = 15, dcox = 7, modx = 0 3 v 16.0 26.0 mhz frequency step between s rsel s rsel = f dco(rsel+1,dco) /f dco(rsel,dco) 3 v 1.35 ratio range rsel and rsel+1 frequency step between s dco s dco = f dco(rsel,dco+1) /f dco(rsel,dco) 3 v 1.08 ratio tap dco and dco+1 duty cycle measured at smclk output 3 v 50 % copyright ? 2012, texas instruments incorporated submit documentation feedback 27
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com calibrated dco frequencies ? tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions t a v cc min typ max unit bcsctl1= calbc1_1mhz, 1-mhz tolerance over dcoctl = caldco_1mhz, -40 c to 125 c 3 v -3 0.5 +3 % temperature (1) calibrated at 30 c and 3 v bcsctl1= calbc1_1mhz, 1-mhz tolerance over v cc dcoctl = caldco_1mhz, 30 c 1.8 v to 3.6 v -3 2 +3 % calibrated at 30 c and 3 v bcsctl1= calbc1_1mhz, 1-mhz tolerance overall dcoctl = caldco_1mhz, -40 c to 125 c 1.8 v to 3.6 v -6 3 +6 % calibrated at 30 c and 3 v bcsctl1= calbc1_8mhz, 8-mhz tolerance over dcoctl = caldco_8mhz, -40 c to 125 c 3 v -3 0.5 +3 % temperature (1) calibrated at 30 c and 3 v bcsctl1= calbc1_8mhz, 8-mhz tolerance over v cc dcoctl = caldco_8mhz, 30 c 2.2 v to 3.6 v -3 2 +3 % calibrated at 30 c and 3 v bcsctl1= calbc1_8mhz, 8-mhz tolerance overall dcoctl = caldco_8mhz, -40 c to 125 c 2.2 v to 3.6 v -6 3 +6 % calibrated at 30 c and 3 v bcsctl1= calbc1_12mhz, 12-mhz tolerance over dcoctl = caldco_12mhz, -40 c to 125 c 3 v -3 0.5 +3 % temperature (1) calibrated at 30 c and 3 v bcsctl1= calbc1_12mhz, 12-mhz tolerance over v cc dcoctl = caldco_12mhz, 30 c 2.7 v to 3.6 v -3 2 +3 % calibrated at 30 c and 3 v bcsctl1= calbc1_12mhz, 12-mhz tolerance overall dcoctl = caldco_12mhz, -40 c to 125 c 2.7 v to 3.6 v -6 3 +6 % calibrated at 30 c and 3 v bcsctl1= calbc1_16mhz, 16-mhz tolerance over dcoctl = caldco_16mhz, -40 c to 125 c 3.3 v -3 0.5 +3 % temperature (1) calibrated at 30 c and 3 v bcsctl1= calbc1_16mhz, 16-mhz tolerance over v cc dcoctl = caldco_16mhz, 30 c 3.3 v to 3.6 v -3 2 +3 % calibrated at 30 c and 3 v bcsctl1= calbc1_16mhz, 16-mhz tolerance overall dcoctl = caldco_16mhz, -40 c to 125 c 3.3 v to 3.6 v -6 3 +6 % calibrated at 30 c and 3 v (1) this is the frequency change from the measured frequency at 30 c over temperature. 28 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 wake-up from lower-power modes (lpm3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit dco clock wake-up time from bcsctl1 = calbc1_1mhz, t dco,lpm3/4 3 v 1.5 s lpm3/4 (1) dcoctl = caldco_1mhz 1/f mclk + t cpu,lpm3/4 cpu wake-up time from lpm3/4 (2) t clock,lpm3/4 (1) the dco clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (mclk or smclk). (2) parameter applicable only if dcoclk is used for mclk. typical characteristics ? dco clock wake-up time from lpm3/4 figure 16. dco wake-up time from lpm3 vs dco frequency copyright ? 2012, texas instruments incorporated submit documentation feedback 29 dco frequency ? mhz 0.10 1.00 10.00 0.10 1.00 10.00 dco wake time ? us rselx = 0...11 rselx = 12...15
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com crystal oscillator, xt1, low-frequency mode (1) (2) over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit lfxt1 oscillator crystal f lfxt1,lf xts = 0, lfxt1sx = 0 or 1 1.8 v to 3.6 v 32768 hz frequency, lf mode 0, 1 lfxt1 oscillator logic level f lfxt1,lf,logic square wave input frequency, xts = 0, xcapx = 0, lfxt1sx = 3 1.8 v to 3.6 v 10000 32768 50000 hz lf mode lfxt1 oscillator logic level xts = 0, xcapx = 0, lfxt1sx = 3, f lfxt1,lf,logic square wave input frequency, 1.8 v to 3.6 v 32768 hz t a = -40 c to 125 c lf mode xts = 0, lfxt1sx = 0, 500 f lfxt1,lf = 32768 hz, c l,eff = 6 pf oscillation allowance for oa lf k ? lf crystals xts = 0, lfxt1sx = 0, 200 f lfxt1,lf = 32768 hz, c l,eff = 12 pf xts = 0, xcapx = 0 1 xts = 0, xcapx = 1 5.5 integrated effective load c l,eff pf capacitance, lf mode (3) xts = 0, xcapx = 2 8.5 xts = 0, xcapx = 3 11 xts = 0, measured at p2.0/aclk, duty cycle lf mode 2.2 v 30 50 70 % f lfxt1,lf = 32768 hz oscillator fault frequency, f fault,lf xts = 0, xcapx = 0, lfxt1sx = 3 (5) 2.2 v 10 10000 hz lf mode (4) (1) to improve emi on the xt1 oscillator, the following guidelines should be observed. ( a) keep the trace between the device and the crystal as short as possible. ( b) design a good ground plane around the oscillator pins. ( c) prevent crosstalk from other clock or data lines into oscillator pins xin and xout. ( d) avoid running pcb traces underneath or adjacent to the xin and xout pins. ( e) use assembly materials and praxis to avoid any parasitic load on the oscillator xin and xout pins. ( f) if conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. ( g) do not route the xout line to the jtag header to support the serial programming adapter as shown in other documentation. this signal is no longer required for the serial programming adapter. (2) crystal oscillator cannot be operated beyond 105 c. parameters are characterized up to t a = 105 c, unless otherwise noted. (3) includes parasitic bond and package capacitance (approximately 2 pf per pin). because the pcb adds additional capacitance, it is recommended to verify the correct load by measuring the aclk frequency. for a correct setup, the effective load capacitance should always match the specification of the used crystal. (4) frequencies below the min specification set the fault flag. frequencies above the max specification do not set the fault flag. frequencies in between might set the flag. (5) measured with logic-level input frequency but also applies to operation with crystals. internal very-low-power low-frequency oscillator (vlo) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter t a v cc min typ max unit -40 c to 85 c 4 12 20 f vlo vlo frequency 3 v khz 125 c 23 df vlo /d t vlo frequency temperature drift (1) -40 c to 125 c 3 v 0.5 %/ c df vlo /dv cc vlo frequency supply voltage drift (2) 25 c 1.8 v to 3.6 v 4 %/v (1) calculated using the box method: (max(-40 c to 125 c) - min(-40 c to 125 c)) / min(-40 c to 125 c) / (125 c - (-40 c)) (2) calculated using the box method: (max(1.8 v to 3.6 v) - min(1.8 v to 3.6 v)) / min(1.8 v to 3.6 v) / (3.6 v - 1.8 v) timer_a over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit smclk f ta timer_a input clock frequency f system mhz duty cycle = 50% 10% t ta,cap timer_a capture timing (1) ta0, ta1 3 v 20 ns (1) parameter characterized up to t a = 105 c, unless otherwise noted. 30 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 usi, universal serial interface (1) over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit external: sclk, f usi usi module clock frequency f system mhz duty cycle = 50% 10% f (sclk) serial clock frequency, slave mode spi slave mode 3 v 6 mhz usi module in i2c mode, v ss v ol,i2c low-level output voltage on sda and scl 3 v v ss v i (olmax) = 1.5 ma + 0.4 (1) parameters are characterized up to t a = 105 c, unless otherwise noted. typical characteristics ? usi low-level output voltage on sda and scl figure 17. usi low-level output voltage vs output current figure 18. usi low-level output voltage vs output current copyright ? 2012, texas instruments incorporated submit documentation feedback 31 v ol ? low-level output voltage ? v 0.0 1.0 2.0 3.0 4.0 5.0 0.0 0.2 0.4 0.6 0.8 1.0 v cc = 2.2 v t a = 25c ol i ? low-level output current ? ma t a = 85c v ol ? low-level output voltage ? v 0.0 1.0 2.0 3.0 4.0 5.0 0.0 0.2 0.4 0.6 0.8 1.0 v cc = 3 v t a = 25c ol i ? low-level output current ? ma t a = 85c
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com 10-bit adc, power supply and input range conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions t a v cc min typ max unit v cc analog supply voltage v ss = 0 v 2.2 3.6 v all ax terminals, analog inputs v ax analog input voltage (2) 3 v 0 v cc v selected in adc10ae register f adc10clk = 5.0 mhz, adc10on = 1, refon = 0, i adc10 adc10 supply current (3) -40 c to 125 c 3 v 0.6 ma adc10sht0 = 1, adc10sht1 = 0, adc10div = 0 f adc10clk = 5.0 mhz, adc10on = 0, ref2_5v = 0, 0.25 refon = 1, refout = 0 reference supply current, i ref+ -40 c to 125 c 3 v ma reference buffer disabled (4) f adc10clk = 5.0 mhz, adc10on = 0, ref2_5v = 1, 0.25 refon = 1, refout = 0 f adc10clk = 5.0 mhz, reference buffer supply adc10on = 0, refon = 1, i refb,0 -40 c to 125 c 3 v 1.1 ma current with adc10sr = 0 (4) ref2_5v = 0, refout = 1, adc10sr = 0 f adc10clk = 5.0 mhz, reference buffer supply adc10on = 0, refon = 1, i refb,1 -40 c to 125 c 3 v 0.5 ma current with adc10sr = 1 (4) ref2_5v = 0, refout = 1, adc10sr = 1 only one terminal ax can be c i input capacitance -40 c to 125 c 3 v 27 pf selected at one time r i input mux on resistance 0 v v ax v cc -40 c to 125 c 3 v 1000 ? (1) the leakage current is defined in the leakage current table with px.x/ax parameter. (2) the analog input voltage range must be within the selected reference voltage range v r+ to v r ? for valid conversion results. (3) the internal reference supply current is not included in current consumption parameter i adc10 . (4) the internal reference current is supplied via terminal v cc . consumption is independent of the adc10on control bit, unless a conversion is active. the refon bit enables the built-in reference to settle before starting an a/d conversion. 32 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 10-bit adc, built-in voltage reference over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit i vref+ 1 ma, ref2_5v = 0 2.2 positive built-in reference v cc,ref+ v analog supply voltage range i vref+ 1 ma, ref2_5v = 1 3 i vref+ i vref+ max, ref2_5v = 0 1.37 1.5 1.61 positive built-in reference v ref+ 3 v v voltage i vref+ i vref+ max, ref2_5v = 1 2.29 2.5 2.7 maximum vref+ load i ld,vref+ 3 v 1 ma current (1) i vref+ = 500 a 100 a, analog input voltage v ax 0.75 v, 2 ref2_5v = 0 vref+ load regulation (1) 3 v lsb i vref+ = 500 a 100 a, analog input voltage v ax 1.25 v, 2 ref2_5v = 1 i vref+ = 100 a 900 a, v ref+ load regulation v ax 0.5 vref+, 3 v 400 ns response time error of conversion result 1 lsb, adc10sr = 0 maximum capacitance at c vref+ i vref+ 1 ma, refon = 1, refout = 1 3 v 100 pf pin vref+ (1) ppm/ tc ref+ temperature coefficient i vref+ = const with 0 ma i vref+ 1 ma 3 v 170 c settling time of internal i vref+ = 0.5 ma, ref2_5v = 0, t refon reference voltage to 99.9% 3.6 v 30 s refon = 0 1 vref i vref+ = 0.5 ma, settling time of reference t refburst ref2_5v = 1, refon = 1, 3 v 2 s buffer to 99.9% vref (1) refburst = 1, adc10sr = 0 (1) minimum and maximum parameters are characterized up to t a = 105 c, unless otherwise noted. copyright ? 2012, texas instruments incorporated submit documentation feedback 33
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com 10-bit adc, external reference (1) over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit veref+ > veref ? , 1.4 v cc sref1 = 1, sref0 = 0 positive external reference input veref+ v voltage range (2) veref ? veref+ v cc ? 0.15 v, 1.4 3 sref1 = 1, sref0 = 1 (3) negative external reference input veref ? veref+ > veref ? 0 1.2 v voltage range (4) differential external reference veref input voltage range, veref+ > veref ? (5) 1.4 v cc v veref = veref+ ? veref ? 0 v veref+ v cc , 1 sref1 = 1, sref0 = 0 i veref+ static input current into veref+ 3 v a 0 v veref+ v cc ? 0.15 v 3 v, 0 sref1 = 1, sref0 = 1 (3) i veref ? static input current into veref ? 0 v veref ? v cc 3 v 1 a (1) the external reference is used during conversion to charge and discharge the capacitance array. the input capacitance, c i , is also the dynamic load for an external reference during conversion. the dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. (2) the accuracy limits the minimum positive external reference voltage. lower reference voltage levels may be applied with reduced accuracy requirements. (3) under this condition the external reference is internally buffered. the reference buffer is active and requires the reference buffer supply current i refb . the current consumption can be limited to the sample and conversion period with reburst = 1. (4) the accuracy limits the maximum negative external reference voltage. higher reference voltage levels may be applied with reduced accuracy requirements. (5) the accuracy limits the minimum external differential reference voltage. lower differential reference voltage levels may be applied with reduced accuracy requirements. 10-bit adc, timing parameters over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit adc10sr = 0 0.45 6.3 adc10 input clock for specified performance of f adc10clk 3 v mhz frequency adc10 linearity parameters adc10sr = 1 0.45 1.5 adc10 built-in oscillator adc10divx = 0, adc10sselx = 0, f adc10osc 3 v 3.35 6.9 mhz frequency f adc10clk = f adc10osc adc10 built-in oscillator, adc10sselx = 0, 3 v 2.06 3.51 f adc10clk = f adc10osc t convert conversion time s 13 f adc10clk from aclk, mclk, or smclk: adc10div adc10sselx 0 1/f adc10clk turn-on settling time of t adc10on see (1) 100 ns the adc (1) the condition is that the error in a conversion started after t adc10on is less than 0.5 lsb. the reference and input signal are already settled. 10-bit adc, linearity parameters over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit e i integral linearity error 3 v 1 lsb e d differential linearity error 3 v 1 lsb e o offset error source impedance r s < 100 ? 3 v 1 lsb e g gain error 3 v 1.1 2 lsb e t total unadjusted error 3 v 2 5 lsb 34 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 10-bit adc, temperature sensor and built-in v mid over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit temperature sensor supply refon = 0, inchx = 0ah, i sensor 3 v 60 a current (1) t a = 25 c tc sensor adc10on = 1, inchx = 0ah (2) 3 v 3.55 mv/ c sample time required if channel adc10on = 1, inchx = 0ah, t sensor(sample) 3 v 30 s 10 is selected (3) error of conversion result 1 lsb i vmid current into divider at channel 11 adc10on = 1, inchx = 0bh 3 v (4) a adc10on = 1, inchx = 0bh, v mid v cc divider at channel 11 3 v 1.5 v v mid 0.5 v cc sample time required if channel adc10on = 1, inchx = 0bh, t vmid(sample) 3 v 1220 ns 11 is selected (5) error of conversion result 1 lsb (1) the sensor current i sensor is consumed if (adc10on = 1 and refon = 1) or (adc10on = 1 and inch = 0ah and sample signal is high). when refon = 1, i sensor is included in i ref+ . when refon = 0, i sensor applies during conversion of the temperature sensor input (inch = 0ah). (2) the following formula can be used to calculate the temperature sensor output voltage: v sensor,typ = tc sensor (273 + t [ c] ) + v offset,sensor [mv] or v sensor,typ = tc sensor t [ c] + v sensor (t a = 0 c) [mv] (3) the typical equivalent impedance of the sensor is 51 k ? . the sample time required includes the sensor-on time t sensor(on) . (4) no additional current is needed. the v mid is used during sampling. (5) the on-time t vmid(on) is included in the sampling time t vmid(sample) ; no additional on time is needed. flash memory (1) (2) over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions v cc min typ max unit v cc(pgm/erase) program and erase supply voltage 2.2 3.6 v f ftg flash timing generator frequency 257 476 khz i pgm supply current from v cc during program 2.2 v, 3.6 v 1 5 ma i erase supply current from v cc during erase 2.2 v, 3.6 v 1 7 ma t cpt cumulative program time (3) 2.2 v, 3.6 v 10 ms t cmerase cumulative mass erase time 2.2 v, 3.6 v 20 ms program and erase endurance -40 c t j 105 c 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time see (4) 30 t ftg t block, 0 block program time for first byte or word see (4) 25 t ftg block program time for each additional t block, 1-63 see (4) 18 t ftg byte or word t block, end block program end-sequence wait time see (4) 6 t ftg t mass erase mass erase time see (4) 10593 t ftg t seg erase segment erase time see (4) 4819 t ftg (1) parameters are characterized up to t a = 105 c unless otherwise noted. (2) additional flash retention documentation located in application report slaa392 . (3) the cumulative program time must not be exceeded when writing to a 64-byte flash block. this parameter applies to all programming methods: individual word/byte write and block write modes. (4) these values are hardwired into the flash controller ' s state machine (t ftg = 1/f ftg ). copyright ? 2012, texas instruments incorporated submit documentation feedback 35
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com ram over recommended ranges of supply voltage and up to operating free-air temperature, t a = 105 c (unless otherwise noted) parameter test conditions min max unit v (ramh) ram retention supply voltage (1) cpu halted 1.6 v (1) this parameter defines the minimum supply voltage v cc when the data in ram remains unchanged. no program execution should happen during this supply voltage condition. jtag and spy-bi-wire interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f sbw spy-bi-wire input frequency 2.2 v 0 20 mhz t sbw,low spy-bi-wire low clock pulse length 2.2 v 0.025 15 s spy-bi-wire enable time t sbw,en 2.2 v 1 s (test high to acceptance of first clock edge (1) ) t sbw,ret spy-bi-wire return to normal operation time t a = -40 c to 105 c 2.2 v 15 100 s f tck tck input frequency (2) 2.2 v 0 5 mhz r internal internal pulldown resistance on test t a = -40 c to 105 c 2.2 v 25 60 90 k ? (1) tools accessing the spy-bi-wire interface need to wait for the maximum t sbw,en time after pulling the test/sbwclk pin high before applying the first sbwclk clock edge. (2) f tck may be restricted to meet the timing requirements of the module selected. jtag fuse (1) t a = 25 c, over recommended ranges of supply voltage (unless otherwise noted) parameter test conditions min max unit v cc(fb) supply voltage during fuse-blow condition t a = 25 c 2.5 v v fb voltage level on test for fuse blow 6 7 v i fb supply current into test during fuse blow 100 ma t fb time to blow fuse 1 ms (1) once the fuse is blown, no further access to the jtag/test, spy-bi-wire, and emulation feature is possible, and jtag is switched to bypass mode. 36 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 pin schematics port p1 pin schematic: p1.0 to p1.2, input/output with schmitt trigger copyright ? 2012, texas instruments incorporated submit documentation feedback 37 to module from module pxout.y dv ss dv cc 1 tax.y taxclk bus keeper en 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxsel2.y 1 0 inchx = y adc10ae0.y to adc10 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y direction0: input 1: output pxdir.y pxsel.y 3 2 1 0 pxsel2.y p1.0/ta0clk/aclk/a0 p1.1/ta0.0/a1 p1.2/ta0.1/a2 0 0
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com table 15. port p1 (p1.0 to p1.2) pin functions control bits / signals (1) pin name (p1.x) x function p1dir.x p1sel.x p1sel2.x p1.0/ p1.x (i/o) i: 0; o: 1 0 0 ta0clk/ 0 ta0.taclk 0 1 0 aclk/ aclk 1 1 0 a0/ a0 x x x pin osc capacitive sensing x 0 1 p1.1/ p1.x (i/o) i: 0; o: 1 0 0 ta0.0/ 1 ta0.0 1 1 0 ta0.cci0a 0 1 0 a1/ a1 x x x pin osc capacitive sensing x 0 1 p1.2/ p1.x (i/o) i: 0; o: 1 0 0 ta0.1/ 2 ta0.1 1 1 0 ta0.cci1a 0 1 0 a2/ a2 x x x pin osc capacitive sensing x 0 1 (1) x = don ' t care 38 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 port p1 pin schematic: p1.3, input/output with schmitt trigger copyright ? 2012, texas instruments incorporated submit documentation feedback 39 p1.3/adc10clk/a3/ vref-/veref- direction0: input 1: output to module from adc10 * pxout.y dv ss dv cc 1 tax.y taxclk bus keeper en 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0,2,3 pxsel2.y pxsel.y 1 0 inchx = y to adc10 to adc10 vref- 1 0 vss sref2 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y adc10ae0.y pxsel2.y
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com table 16. port p1 (p1.3) pin functions control bits / signals (1) pin name x function adc10ae.x (p1.x) p1dir.x p1sel.x p1sel2.x (inch.x=1) p1.3/ p1.x (i/o) i: 0; o: 1 0 0 0 adc10clk/ adc10clk 1 1 0 0 a3/ a3 x x x 1 (y = 3) 3 vref-/ vref- x x x 1 veref-/ veref- x x x 1 pin osc capacitive sensing x 0 1 0 (1) x = don ' t care 40 submit documentation feedback copyright ? 2012, texas instruments incorporated
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 port p1 pin schematic: p1.4, input/output with schmitt trigger table 17. port p1 (p1.4) pin functions control bits / signals (1) pin name (p1.x) x function adc10ae.x p1dir.x p1sel.x p1sel2.x jtag mode (inch.x=1) p1.4/ p1.x (i/o) i: 0; o: 1 0 0 0 0 smclk/ smclk 1 1 0 0 0 ta0.2/ ta0.2 1 1 1 0 0 ta0.cci2a 0 1 1 0 0 vref+/ 4 vref+ x x x 1 0 veref+/ veref+ x x x 1 0 a4/ a4 x x x 1 (y = 4) 0 tck/ tck x x x 0 1 pin osc capacitive sensing x 0 1 0 0 (1) x = don ' t care copyright ? 2012, texas instruments incorporated submit documentation feedback 41 p1.4/smclk/ta0.2/a4/ vref+/veref+/tck direction0: input 1: output to module smclk pxout.y dv ss dv cc 1 tax.y taxclk bus keeper en 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0 pxsel2.y pxsel.y 1 0 inchx = y to adc10 from/to adc10 ref+ pxsel.y 1 3 2 1 0 pxsel2.y from jtag to jtag pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y adc10ae0.y from timer
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com port p1 pin schematic: p1.5 to p1.7, input/output with schmitt trigger 42 submit documentation feedback copyright ? 2012, texas instruments incorporated p1.5/ta0.0/sclk/a5/tms p1.6/ta0.1/sdo/scl/a6/tdi/tclk p1.7//sdi/sda/a7/tdo/tdi to module from module pxout.y dv ss dv cc 1 tax.y taxclk bus keeper en 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxsel2.y 1 0 inchx = y to adc10 pxsel.y 1 3 2 1 0 pxsel2.y from jtag to jtag pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y direction0: input 1: output pxdir.y from module pxsel.y 3 2 1 0 pxsel2.y adc10ae0.y 0
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 table 18. port p1 (p1.5 to p1.7) pin functions control bits / signals (1) pin name x function adc10ae.x (p1.x) p1dir.x p1sel.x p1sel2.x usip.x jtag mode (inch.x=1) p1.5/ p1.x (i/o) i: 0; o: 1 0 0 0 0 0 ta0.0/ ta0.0 1 1 0 0 0 0 sclk/ spi mode from usi 1 0 1 0 0 5 a5/ a5 x x x 0 0 1 (y = 5) tms/ tms x x x 0 1 0 pin osc capacitive sensing x 0 1 0 0 0 p1.6/ p1.x (i/o) i: 0; o: 1 0 0 0 0 0 ta0.1/ ta0.1 1 1 0 0 0 0 sdo/ spi mode from usi 1 0 ! 0 0 scl/ 6 i2c mode from usi 1 0 ! 0 0 a6/ a6 x x x 0 0 1 (y = 6) tdi/tclk/ tdi/tclk x x x 0 1 0 pin osc capacitive sensing x 0 1 0 0 0 p1.7/ p1.x (i/o) i: 0; o: 1 0 0 0 0 0 sdi/ spi mode from usi 1 0 1 0 0 sda/ spi mode from usi 1 0 1 0 0 7 a7/ a7 x x x 0 0 1 (y = 7) tdo/tdi/ tdo/tdi x x x 0 1 0 pin osc capacitive sensing x 0 1 0 0 0 (1) x = don ' t care copyright ? 2012, texas instruments incorporated submit documentation feedback 43
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com port p2 pin schematic: p2.0 to p2.5, input/output with schmitt trigger 44 submit documentation feedback copyright ? 2012, texas instruments incorporated p2.0p2.1 p2.2 p2.3 p2.4 p2.5 direction0: input 1: output to module pxout.y dv ss dv cc 1 tax.y taxclk 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxsel2.y 1 0 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y pxdir.y 1 0 pxsel.y 0 0
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 table 19. port p2 (p2.0 to p2.5) pin functions control bits / signals (1) pin name x function (p2.x) p2dir.x p2sel.x p2sel2.x p2.0/ p2.x (i/o) i: 0; o: 1 0 0 0 pin osc capacitive sensing x 0 1 p2.1/ p2.x (i/o) i: 0; o: 1 0 0 1 pin osc capacitive sensing x 0 1 p2.2/ p2.x (i/o) i: 0; o: 1 0 0 2 pin osc capacitive sensing x 0 1 p2.3/ p2.x (i/o) i: 0; o: 1 0 0 3 pin osc capacitive sensing x 0 1 p2.4/ p2.x (i/o) i: 0; o: 1 0 0 4 pin osc capacitive sensing x 0 1 p2.5/ p2.x (i/o) i: 0; o: 1 0 0 5 pin osc capacitive sensing x 0 1 (1) x = don ' t care copyright ? 2012, texas instruments incorporated submit documentation feedback 45
MSP430G2332-EP slas885a ? august 2012 ? revised october 2012 www.ti.com port p2 pin schematic: p2.6, input/output with schmitt trigger table 20. port p2 (p2.6) pin functions control bits / signals (1) pin name x function p2sel.6 p2sel2.6 (p2.x) p2dir.x p2sel.7 p2sel2.7 1 0 xin/ xin 0 1 0 0 0 p2.6/ p2.x (i/o) i: 0; o: 1 x 0 6 1 0 ta0.1/ timer0_a3.ta1 1 0 0 0 1 pin osc capacitive sensing x x x (1) x = don ' t care 46 submit documentation feedback copyright ? 2012, texas instruments incorporated xin/p2.6/ta0.1 direction0: input 1: output to module from module pxout.y dv ss dv cc 1 tax.y taxclk 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0 pxsel2.y pxsel.y 1 0 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y 1 0 xout/p2.7 lf off lfxt1clk pxsel.6 & pxsel.7 bcsctl3.lfxt1sx = 11 0
MSP430G2332-EP www.ti.com slas885a ? august 2012 ? revised october 2012 port p2 pin schematic: p2.7, input/output with schmitt trigger table 21. port p2 (p2.7) pin functions control bits / signals (1) pin name x function p2sel.6 p2sel2.6 (p2.x) p2dir.x p2sel.7 p2sel2.7 1 0 xout/ xout x 1 0 x 0 p2.7/ 7 p2.x (i/o) i: 0; o: 1 0 0 x x pin osc capacitive sensing x 0 1 (1) x = don ' t care copyright ? 2012, texas instruments incorporated submit documentation feedback 47 xout/p2.7 direction0: input 1: output to module from module pxout.y dv ss dv cc 1 tax.y taxclk 1 0 pxin.y en d pxsel.y pxren.y 1 0 pxdir.y 1 0 pxsel2.y pxsel.y 1 0 pxsel.y 1 3 2 1 0 pxsel2.y pxirq.y pxie.y en set q interrupt edge select pxsel.y pxies.y pxifg.y 1 0 xin/p2.6/ta0.1 lf off lfxt1clk pxsel.6 & pxsel.7 bcsctl3.lfxt1sx = 11 from p2.6
package option addendum www.ti.com 4-sep-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430g2332qpw2ep active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 g2332ep msp430g2332qpw2rep active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 g2332ep v62/12625-01xe active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 g2332ep v62/12625-01xe-t active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 g2332ep (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 4-sep-2014 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of MSP430G2332-EP : ? catalog: msp430g2332 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430g2332qpw2rep tssop pw 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 package materials information www.ti.com 22-mar-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) msp430g2332qpw2rep tssop pw 20 2000 367.0 367.0 38.0 package materials information www.ti.com 22-mar-2014 pack materials-page 2

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